Multiple low-speed into single high-speed sdh/sonet channel mapper/framer device and method

ABSTRACT

According to the present invention a method and a device is provided for combining at least two data signals having a first data rate into a single data stream having a second data rate being higher than the first data rate for transmission on a shared medium or vice versa, said device comprises at least one port for receiving said at least two data signals and a port addressing unit for extracting data from the data signals received by said ports, wherein said port addressing unit is configured to place the extracted data at predetermined positions in said single data stream to be transmitted on said shared medium and at least one control data insertion unit is provided for placing control data in said single data stream. Thus, a method and device proposed implementing a multiplexing structure in which the data from M parallel low-speed channels are multiplexed onto a data bus operating with M times the data rate of the M low-speed channels. A multiple-stage process where, e.g., 28 T-1 (DS-1) channels are re-mapped into one T-3 (DS-3) channel and 3 T-3 (DS-3) channels are then mapped into an STM- 1  frame is advantageously avoided.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method and device forcombining at least two data signals having a first data rate into asingle data stream having a second data rate being higher than the firstdata rate for transmission on a shared medium and vice versa.Particularly, the present invention relates to a method and device forcombining 84 T-1 (DS-1) channels of 1.544 Mb/s (megabits per second)each into one STM-1 frame corresponding to 155 Mb/s and 63 E-1 channelsof 2.048 Mb/s each or 21 T-2 (DS-2) channels of 6.312 Mb/s each into oneSTM-1 frame, respectively. However, the concept of the present inventionis also applicable for different protocols or other hierarchical levelsof the SDH or SONET standard as apparent from the following description.

[0003] 2. Description of the Related Art

[0004] The American National Standards Institute has established astandard for high-speed, multiplexed digital data transmission. This isthe “synchronous optical network” standard, henceforth referred to asSONET. The SONET standard specifies optical interfaces, data rates,operation procedures and frame structures for multiplexed digitaltransmission via fiber optic networks.

[0005] The International Telecommunications Union (ITU) has adopted theInterface principles of SONET and recommended a new global transmissionstandard for high-speed digital data transmission. This standard is the“synchronous digital hierarchy” (SDH).

[0006] For an account of the SDH standard, reference should be made tothe report 30 entitled “REPORT OF Q.22/15 MEETING” from “STUDY GROUP 15”of the ITU International Telecommunication Standardization Sector,bearing the document number “Temporary Document 62(3/15)” and the date“Geneva, 16-27 May 1994.11

[0007] The SDH standard is designed to enable manufacturers to developtelecommunications equipment which:

[0008] a) will be interchangeable in all telecommunication networksbuilt around the world to its standard; and which

[0009] b) is backwards compatible, i.e. can be used with data which isin the older telecommunications formats used in North America, Europeand Japan.

[0010] This is achieved by a complex hierarchy of so-called “Containers”(C) and “Virtual Containers” (VC), see FIG. 1. The container, e.g. C-4,C-3, C-12, etc., are information structures designed to accommodate datatraffic with specific transmission rates. The C-4 carries traffic with abase rate of up to 139264 kbit/s, the C-3 container carries either up to44736 or 34368 kbit/s, etc. The containers are turned into virtualcontainers by adding Path Overhead information (POH) to it. Byprocedures defined as multiplexing, mapping, or aligning, datastructures are generated which are constitutive to the SDH. These datastructures are named “Administrative Unit Groups” (AUG) and “SynchronousTransport Module” (STM). The label of an STM is defined by the number ofAUGs it carries: a STM-4 contains for example four AUGs. An AUG containseither one “Administration Unit” (AU) of type AU-4 or three of typeAU-3. Referring to the simplest cases, in turn one AU-4 contains one C-4signal and one AU-3 carries one C-3 signal.

[0011] The SDH/SONET data frames, i.e., the STM-N signals, are 125Microseconds long. The amount of data transmitted in each frame dependson the hierarchy level N of the signal. The higher hierarchical levelsare transmitted at higher data rates than the basic STM-1 level ofapproximately 155 Mbit/s. The exact transmission rate is defined as155.52 Mbit/s. However, here and in the following transmission rates areoften denoted by their approximate values. This is, in particular, dueto the fact that the exact data transmission rates are distorted byoverhead data traffic and idle cell stuffing. The integer N indicateshow many times faster the data is transmitted than in the STM-1 level.For example STM-4 denotes a data transmission rate of 622 Mbit/s,whereby each data frame contains four times as many bytes as does aframe of STM-1. The highest defined level is STM-64, which has a datarate of 9.95 Gb/s. Hence, each part of the STM-N signal is broadcast inthe same time as the corresponding part of an STM-1 signal, but containsN times as many bytes.

[0012] The STM-1 signal, as shown in FIG. 2, contains an informationrectangle of 9 rows with 270 bytes/row corresponding to a SONET/SDH datarate of 155.52 Mbit/s. The first 9 bytes/row represent the “SectionOverhead” henceforth SOH. The remaining 261 bytes/row are reserved forthe VCs, which in FIG. 1 is a VC-4. The first column of a VC-4 containerconsists of the “Path Overhead” (POH). The rest is occupied by thepayload (a C-4 signal). Several VCs can be concatenated to provide asingle transmission channel with a corresponding bandwidth. For example,four VC-4 in a STM-4 signal can be concatenated to form a single datachannel with approximately 600 Mbit/s capacity: in this case the fourVCs are referred to in the standard terminology as VC-4-4c and thesignal as STM-4c.

[0013] This flexibility of the SDH standard is partly due to the pointerconcept: In SDH, the frames are synchronized, but the VCs within themare not locked to the frames. So the individual containers of the SDHsignals do not have to be frame aligned or synchronized amongst eachother. A “pointer” is provided in the Section Overhead which indicatesthe position of the above introduced POH, i.e., the start of a virtualcontainer in the SDH frame. The POH can thus be flexibly positioned atany position in the frame. The multiplexing of information into higherorder SDH frames becomes simpler than in the old data standards, and anexpensive synchronization buffer is not required in SDH. Similarly,lower order signals can be extracted out of and inserted into the higherorder SDH signals without the need to demultiplex the entire signalhierarchy. The pointers are stored in the fourth row of the SectionOverhead.

[0014] The Section Overhead is further subdivided into: (i) The“Regenerator Section Overhead” or RSOH. This portion contains bytes ofinformation which are used by repeater stations along the routetraversed by the SONET/SDH Signal. The Regenerator Section Overheadoccupies rows 1-3 of the Section Overhead. (ii) The “Multiplexer SectionOverhead” or MSOH. This contains bytes of information used by themultiplexers along the SONET/SDH signal's route. The Multiplexer SectionOverhead occupies rows 5-9 of the Section Overhead. These sections ofthe overhead are assembled and dissembled at different stages during thetransmission process. FIG. 2 also shows an exploded view of the MSOH.

[0015] In the parallel SONET system, a base signal of 51.84 Mbit/s isused. It is called the Synchronous Transport Signal level 1, henceforthSTS-1. This has an information rectangle of 9 rows with 90 bytes/row.The first three bytes/row are the section overhead and the remaining 87bytes/row are the “synchronous payload envelope”, henceforth SPE. Threeof these SPEs fit exactly into one Virtual Container-4. Thus signals inthe STS-1 signal format can be mapped into an STM-1 frame. Furthermore,frame aligned STS-1 or STM-1 signals can be multiplexed into higherorder STM-N frames.

[0016] In general, any lower data rate signal which is combined withother such signals into new data frames of higher rate is referred to asa “tributary” signal. For example in the previous paragraph, the threeSTS-1 signals which are combined into one STM-1 signal are tributarysignals. It may be noted that the scope of the term tributary in thisdescription exceeds the standard definition, as it is also used todescribe the inter-level signal mapping in SDH.

[0017] The present invention relates to a data processing module formapping data, i.e. tributaries, into and out of the SDH/SONET formats.The data processing achieved with the present invention concerns inparticular the compilation of data which is at relatively low data ratesinto standard data frames of relatively high data rate, and vice-versa.U.S. Pat. No. 5,452,307 describes a general data multiplexing systemcomprising a plurality of data multiplexing buses through which aplurality of low-speed digital signals are collected into, anddistributed from, a multiplexer/demultiplexer. In a data multiplexingmode, the low-speed digital signals entered from a plurality oflow-speed transmission lines have their signal format converted byrespectively corresponding low-speed interface circuits, and theresulting signals are multiplexed in time slots designated within amultiplexed signal of primary level on the up bus line of thecorresponding data multiplexing bus, under the controls of respectivelycorresponding bus control circuits. The high-speed multiplexer collectsthe primary multiplexed signals on the up bus lines of the plurality ofdata multiplexing buses, and further multiplexes the collected signalsup to a predetermined signal level. Thereafter, it sends the resultingsecondary multiplexed signal to a high-speed interface module having ahigh-speed transmission line interface. The high-speed interface moduleconverts the received secondary multiplexed signal so as to match theinterface of a high-speed transmission line, and sends the resultingsignal to the high-speed transmission line. In a data demultiplexingmode, the signal of the high-speed transmission line is processed by thehigh-speed interface module and the high-speed demultiplexer, and theresulting signals are distributed through the down bus lines of the datamultiplexing buses so as to send the low-speed digital signals to thelow-speed transmission lines.

[0018] In M. Stadler et. al., “An Embedded Stack Microprocessor for SDHTelecommunication Applications”, in Proceedings of the IEEE 1998 CustomIntegrated Circuits Conference (CICC'98), Santa Clara, Calif., USA, May11-14, 1998, a microprocessor is disclosed which is integrated on thesame die as the complete data path of a SDH Add-Drop Multiplexer (ADM).It handles over 1 Million interrupts per second from 29 asynchronoussources. The multiple asynchronous data sources are each connectedeither to multiple VC-3 mapping units (also called “mapper”) or tomultiple VC-12 mapping units for overhead processing. On one hand, eachVC-3 mapping unit is coupled to a TU-3 framing unit (also called“framer”) that also takes care of the pointer processing in order tofacilitate the frequency adaption between the asynchronous data sourcesand the clock rate of the higher hierarchy levels. On the other hand,each VC-12 mapping unit is linked to a TU-12 framing unit that alsotakes care of the pointer processing in order to facilitate thefrequency adaption between the asynchronous data sources and the clockrate of the higher hierarchy levels. Subsequently, all TU-3 and TU-12framing units are combined into one data stream by a VC-4 mapping unitthat itself is linked to a AU-4 framing unit for pointer processing and,thereafter, the data steam reaches a STM-1 framing unit, between eachframing or mapping unit a different frequency area being realized.

[0019] With the increasing mix of voice and data on SDH/SONET networksthere is a huge need for mapping low-speed plesiochronous digitalhierarchy (PDH), i.e., a transmission system for voice communicationusing plesiochronous synchronization, channels into high-speedsynchronous digital hierarchy (SDH) frames. This is presently done in asystem such as the described above in M. Stadler et. al.

[0020] European patent application EP 0 874 487 A2 discloses a method,in which at least two data signals having a first data rate aremultiplexed into a single data stream having a second data rate beinghigher than the first data rate for transmission on a shared medium orvice versa. Supercarrier control signals are generated. A supercarriertransmitter maps the supercarrier data signals and the supercarriercontrol signals into an output supercarrier signal of a high bit rate,and transmits same over high rate span. However, European patentapplication EP 0 874 487 A2 does not disclose a detailed solution foroffering complete SDH/SONET processing for M low-speed channels in asingle line of processing units operating at M times the speed of thelow channels without the need of any further buffer in the data pathbehind the ports. Therefore it is difficult to implement the wholedevice using one single integrated circuit. Thus, it is a problem toconstruct the device with all its memories on one and the same chip.

[0021] Starting from this, it is an object of the present invention toprovide a method and device to more efficiently perform the function ofcombining at least two data signals having a first data rate into asingle data stream having a second data rate being higher than the firstdata rate for transmission on a shared medium and vice versa.

BRIEF SUMMARY OF THE INVENTION

[0022] The foregoing object is achieved by a method and a system as laidout in the independent claims. Further advantageous embodiments of thepresent invention are described in the sub claims and are taught in thefollowing description.

[0023] According to the present invention a method and a device isprovided for combining at least two data signals having a first datarate into a single data stream having a second data rate being higherthan the first data rate for transmission on a shared medium or viceversa, said device comprises at least one port for receiving said atleast two data signals and a port addressing unit for extracting datafrom the data signals received by said ports, wherein said portaddressing unit is configured to place the extracted data atpredetermined positions in said single data stream to be transmitted onsaid shared medium and at least one control data insertion unit isprovided for placing control data in said single data stream.

[0024] Thus, a method and device proposed implementing a multiplexingstructure in which the data from M parallel low-speed channels aremultiplexed onto a data bus operating with M times the data rate of theM low-speed channels. A multiple-stage process where, e.g., 28 T-1(DS-1) channels are re-mapped into one T-3 (DS-3) channel and 3 T-3(DS-3) channels are then mapped into an STM-1 frame is advantageouslyavoided. However, it extents beyond simple multiplexing, since accordingto the present invention the data to be transmitted are fully processedin accordance with the applied protocol, e.g., SDH/SONET, in one go.Hence, the present invention teaches full SDH/SONET processing of thedata and not only data multiplexing.

[0025] In order to facilitate full processing as aforementioned the dataare augmented by additional control data which represent an encoding ofthe port number on which the corresponding data arrive (multiplexdirection) or to which the data must be send (demultiplex direction).Furthermore, control data such as path overhead information and sectionoverhead information, including regenerator section overhead andmultiplexer section overhead, are placed in the data stream. In case thecontrol data are dependent on the data to be transmitted, also called.“workload”, the control data insertion unit may be configured to atleast partly derive said control data from said data positioned in saiddata stream.

[0026] In a preferred embodiment of the present invention the controldata insertion unit is configured to place the extracted data into saidsingle data stream according to a predetermined transmission protocol,such as SONET or SDH. Alternatively or in addition, the port addressingunit may be configured to place the extracted data into said single datastream according to a predetermined transmission protocol, such as SONETor SDH.

[0027] By applying the concept of the present invention to, e.g., amultiple low-speed into single high-speed SDH/SONET channelmapper/framer device and method, it is possible to offer completeSDH/SONET processing for M low-speed channels in a single line ofprocessing units operating at M times the speed of the low-speedchannels is possible. Advantageously, employing in parallel M suchprocessing lines each at the speed of the low-speed channels can beomitted. The system clock rate has to be sufficient, e.g., for STM-1speed (or even up to STM-64 speed). Although there is a high number oflow-speed channels, e.g., 84, the clock rate is sufficient serving alllow-speed channels.

[0028] In other words, the present invention provides a method anddevice which advantageously implements a single data path at STM-1 speedinstead of implementing, e.g., 84 parallel data paths at 1.544 Mb/sspeed. This reduces manufacturing costs. Furthermore, all portions ofthe device are accordingly driven by the same system clock.

[0029] Each processing unit in the data path is storing the necessaryinformation for data processing in a set of registers identified by theencoded port number. Which each clock cycle the new data is processedaccording to the information stored for the corresponding port number.The information needed to store is the corresponding overhead bytes inthe units which do VC mapping plus a counter which identifies the actualposition in the corresponding frame. The storage needed for the overheadbytes for VC-11, VC-12 and VC-2 containers is preferably provided on thesame chip without an external memory.

[0030] In another preferred embodiment of the present invention, thedevice further comprises at least one buffer for buffering the datareceived by said at least one port, whereby, preferably, the at leastone buffer is formed by a FIFO. Generally, it is sufficient, to providea buffer having the capacity of storing two bytes, since in a SDH/SONETenvironment the data are handled byte-wise. However, it might beadvantageous to increase the input buffer in order to use it for pointergeneration in accordance with a predetermined transmission protocol,such as SONET or SDH.

[0031] In order to provide flexible digital cross-connect and add/dropmultiplexing functionality between channels the port addressing unit ispreferably configured to extract data from said ports in a predeterminedorder.

[0032] The present invention can be realized in hardware, software, or acombination of hardware and software. Any kind of computer system—orother apparatus adapted for carrying out the methods described herein—issuited. A typical combination of hardware and software could be ageneral purpose computer system with a computer program that, when beingloaded and executed, controls the computer system such that it carriesout the methods described herein. The present invention can also beembedded in a computer program product, which comprises all the featuresenabling the implementation of the methods described herein, andwhich—when loaded in a computer system—is able to carry out thesemethods.

[0033] Computer program means or computer program in the present contextmean any expression, in any language, code or notation, of a set ofinstructions intended to cause a system having an information processingcapability to perform a particular function either directly or aftereither or both of the following a) conversion to another language, codeor notation; b) reproduction in a different material form.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0034] The above, as well as additional objectives, features andadvantages of the present invention, will be apparent in the followingdetailed written description.

[0035] The novel features of the invention are set forth in the appendedclaims. The invention itself, however, as well as a preferred mode ofuse, further objectives, and advantages thereof, will best be understoodby reference to the following detailed description of an illustrativeembodiment when read in conjunction with the accompanying drawings,wherein:

[0036]FIG. 1 shows an overview over the SDH signal hierarchy up to theSTM-N signal;

[0037]FIG. 2 shows a STM-1 signal with a VC-4 container according tostandard provisions;

[0038]FIG. 3 shows a device for combining multiple data signals having afirst data rate into a single data stream having a second data ratebeing higher than the first data rate for transmission on a sharedmedium according to the present invention in form of a multiple T1/E1 tosingle STM-1 mapper

DETAILED DESCRIPTION OF THE INVENTION

[0039] With reference to FIG. 3, there is depicted a device 100 forcombining multiple data signals having a first data rate into a singledata stream having a second data rate being higher than the first datarate for transmission on a shared medium according to the presentinvention in form of a multiple T1/E1 to single STM-1 mapper. Each ofsaid multiple data signals enter the device through ports 102 to 108. Incase that the device also functions in the demultiplex direction, theports are also used to write data signal back to the respective lines(not shown). For the sake of clarity not all of the ports needed for animplementation as described below are shown. In fact, any number ofports could be used to implement a device in accordance with the conceptof the present invention. In the present case, however, a multiple T1/E1to STM-1 SDH/SONET mapper is shown which allows mapping of 84 T1 (SONETstandard, 1.5 Mb/s) or 63 El (SDH standard, 2 Mb/s). The straight linesdrawn between ports 104, 106 and 106, 108 symbolizes the omittedrectangles for the remaining ports.

[0040] A data bus 110 connects the ports 102 to 108 with a portaddressing unit 112. On one hand, the port addressing unit 112communicates over a data link 114 with one or more memory units 114 thatare used to temporarily store data received from the ports 102 to 108.On the other hand, the port addressing unit 112 transmits or receivesthrough line 118 data to or from a TU-11 framer 120. Subsequently, fromthe TU-11 framer 120 the data are forwarded to and returned fromTUG-2/TUG-3/VC-4 mapper 122 over line 124, respectively, depending onthe mode of operation, muliplex-mode or demuliplex-mode. It isacknowledged that the TUG-2/TUG-3/VC-4 mapper 122 may also be split intoa TUG-2 mapper, a TUG-3 mapper and a VC-4 mapper. Likewise, otherportions of the described device may be merged into one functional unit.Independently from the functional point of view, the whole device ispreferably implemented using on single integrated circuit. The TU-11framer 120 and the TUG-2/TUG-3/VC-4 mapper 122 function as an datainsertion unit in the sense that they apply control data to the datastream to be transmitted.

[0041] In the next level the data from the TUG-2/TUG-3/VC-4 mapper 122are fed into a STM-1 framer 126 through connection 128. From the STM-1framer 126 the data stream reaches said shared medium (not shown) fortransmitting the data received by the ports or vice versa. The sharedmedium is, e.g., an optical fibre. Thus the device according to FIG. 1combines 84 T1 (SONET standard, 1.5 Mb/s) or 63 El (SDH standard, 2Mb/s) channels into a single VC-4 container and finally an STM-1 (OC-3)frame.

[0042] The port addressing unit 112 accesses in read or write mode theports 102 to 108 one by one in order to get and send data, respectively.The order in which the ports are accessed may be random, however, if itis desired to assign the same input ports in a multiplexing mode toidentical output ports in demulitplexing mode, the order in which thedifferent channels are mulitplexed need to be identical to the order ofdemultiplexing. In case one channel is meant to be directed from oneport onto another port the order of the port access in the multiplexingmode and demulitplexing mode needs to differ respectively.

[0043] Together with a STM-1 to STM-64 (OC-3 to OC-192) framer accordingto the SDH/SONET standard the device according to the present inventioncan be used to enable STM-64 (OC-192) frame handling with achannelization down to T1 level, including digital cross-connect andadd/drop multiplexing functionality between all channels. The mapper isadvantageously implemented using a data multiplexing or contextswitching architecture.

[0044] The data path width for the mapper is chosen as 1 byte. The unitsfor VC-11/VC-12 framing and TU-11/TU-12 processing are designed in thedata multiplexing or context switching architecture. Hence, these unitswork on 1 byte from a single T1/E1 channel at one clock cycle and on acorresponding byte from another T1/E1 channel in the next clock cycle.The corresponding parameters per channel are stored in the memory blocks116. The System clock is running at STM-1 rate for a 1 byte data pathwidth. The TUG-2/TUG-3 mapper unit maps these 84 TU-11 or 63 TU-12frames into 21 TUG-2 frames and these into 3 TUG-3 frames and thesefinally into a single data stream which is the payload for the VC-4container. The VC-4 framer maps this data stream into a single VC-4container and the STM-1 framer maps this into a AU-4 unit and finallyinto an STM-1 frame. The reverse direction is done accordingly. However,the design of the VC-4 and STM-1 framer units may also not in the datamultiplexing or context switching architecture.

[0045] Pointer processing is required at two points, at the TU-11/TU-12level and at the AU-4 level. Pointer generation at the AU-4 level may beskipped since any clock rate adaptation is already solved at theTU-11/TU-12 level and the VC-4/STM-1 units are running with the sameclock as the TU-11/TU-12 units. Pointer interpretation, however, isneeded on both levels since received STM-1 frames with VC-11/VC-12 unitsmay have been created in a very different way by other mappers.

[0046] The mapper should have an STM-1 (OC-3) line interface as well asan interface for VC-4 containers directly. The VC-4 interface allowsexchange of VC-4 containers in both directions with the planned STM-1 toSTM-64 (OC-3 to OC-192) framer and thereby enables mapping of T1/E1channels into OC-192 frames and digital cross-connect between allchannels down to the T1 level.

[0047] In the following the conversion from T1/E1 to STM-1 is described.There are two alternatives to realize the 84 T1 or 63 E1 ports. One wayis to include 84 or 63 PLLs (Phase Locked Loop) on the chip. A simpleserial data stream is received at each port and clock/data recovery isdone at each port or each port receives serial data plus recovered clockfrom the I/O module. An approach to include 63 PLLs on a chip may isknown from the aforementioned document written by M. Stadler et. al., inwhich a corresponding chip is described handling 63 El channels in anarchitecture with 63 parallel VC-12 and TU-12 processing units plus aspecial embedded stack microprocessor for handling all overhead byteprocessing.

[0048] Each port needs a small FIFO to buffer at least 2 bytes ofincoming data. However, it may be better to enlarge the buffer so thatthe buffering for pointer generation is done with this buffer too. Inthis case, all the units above the buffer can run with the STM-1 systemclock, any frequency adaptation is done within the buffer unit. Theinclusion of VC-1 POH and STM-1 SOH bytes (and fixed stuff bytes) intothe data stream can then be achieved by using clock cycles which do notread data bytes from the buffer whenever overhead bytes must beinserted. The overhead bytes are then written into these empty spaces inthe data sequence. This is possible since the whole system runs with asingle clock and clock rate adaptation is done in the port buffer, i.e.,the position of all overhead bytes is known in advance.

[0049] In a second step, the port addressing unit reads 1 byte of datafrom each port-buffer in a predefined sequence. Digital cross-connectfunctionality on VC-11/VC-12 level is achieved by changing this sequenceand hence the position of the VC-11/VC-12 in the final VC-4.

[0050] Thirdly, after the port addressing unit a frame-byte alignmentunit is provided which ensures that each 8-bit portion on the data pathis really 1 byte of the corresponding T1/E1 channel.

[0051] In a fourth step, in a VC-11/VC-12 overhead processor unit therequired VC-1 path overhead bytes (V5, J2, Z6 and Z7) per port areincluded into the data stream. The VC-12 consists of the VC-1 POH plus1023 data bits, six justification control bits, two justificationopportunity bits, eight overhead communication channel bits, fixed stuffbits and bits reserved for future overhead communication purposes. TheVC-11 consists of the VC-1 POH plus 771 data bits, six justificationcontrol bits, two justification opportunity bits, eight overheadcommunication channel bits, fixed stuff bits and bits reserved forfuture overhead communication purposes. The T1/E1 data can be mappedinto the VC-11/VC-12 in an asynchronous mode, a bit-synchronous mode anda byte-synchronous mode.

[0052] In a fifth step, the TU-11/TU-12 unit then is responsible forpointer generation according to the buffer filling at receive line ratein respect to the data extraction from the corresponding port-buffer atSystem clock rate. The TU-11/TU-12 pointer points to the V5 byte of theVC-1 POH. The V5 byte is the first byte of the multiframe.

[0053] Next, the TUG-2/TUG-3/VC-4 mapper then maps the incoming bytedata stream into 1 VC-4 container which contains 3 TUG-3 frames whicheach contains 7 TUG-2 frames which each contains either 4 TU-11 units or3 TU-12 units. The TUG-3 is a 9-row by 86 column structure. 3 TUG-3s arethen mapped into the 9-row by 261 column VC-4 with the followingsequence of columns

[0054] 1. VC-4 POH

[0055] 2. fixed stuff

[0056] 3. fixed stuff

[0057] 4. first column of first TUG-3

[0058] 5. first column of second TUG-3

[0059] 6. first column of third TUG-3

[0060] 7. second column of first TUG-3

[0061] 8. second column of second TUG-3

[0062] . . .

[0063] 259. 86th column of first TUG-3

[0064] 260. 86th column of second TUG-3

[0065] 261. 86th column of third TUG-3

[0066] Each TUG-3 starts with 2 columns of fixed stuff followed by thebyte-interleaved columns of the 7 TUG-2s it contains. Each TUG-2consists of the columns of 4 byte-interleaved TU-11 or 3byte-interleaved TU-12 without additional fixed stuff or overhead bytes.In total, each of the 261 columns of the VC-4 corresponds exactly to acorresponding column of a specific TU-11/TU-12 or to fixed stuff or toVC-4 POH. Hence, by reading 1-byte words from the FIFO buffer of eachport in the correct sequence and filling in the required overhead andfixed stuff bytes one arrives at the correct VC-4 without the need forany further buffers in the data path. In principle this could beextended even up to the STM-1 frame. However, since it is desired tohave the possibility to send VC-4s to the OC-3 to OC-192 framer and notjust complete STM-1 frames, the STM-1 framer unit is kept separated fromthe TUG-2/TUG-3/VC-4 mapper unit with a buffer between both units.

[0067] Finally, the STM-1 framer creates the STM-1 frame from the VC-4by including the corresponding overhead bytes. No pointer generation isneeded here since all frequency adaptation was already done at theTU-11/TU-12 level. Accordingly the AU-4 pointer value will be fixed atzero.

[0068] In the following the procedure from STM-1/VC-4 to T1/E1 isdescribed. Firstly, the STM-1 framer has to do AU-4 pointerinterpretation and section overhead bytes processing.

[0069] In a second step, the VC-4/TUG-3/TUG-2 framer either receives theVC-4 from the STM-1 framer or directly through an external interface tothe OC-3 to OC-192 framer. The framer processes the VC-4 POH bytes andforwards all TU-11/TU-12 overhead and data bytes towards the TU-11/TU-12unit. Fixed stuff and VC-4 POH bytes are not forwarded.

[0070] Thirdly, the TU-11/TU-12 unit interprets the TU-11/TU-12 pointervalues and forwards the data to the VC-11/VC-12 framer unit.

[0071] In a fourth step, the VC-11/VC-12 framer unit processes allVC-11/VC-12 overhead bytes and forwards the data without overhead andfixed stuff bytes/bits to the port addressing unit.

[0072] Finally, the port addressing unit sends the data to thecorresponding output port buffer.

[0073] The arrangement of the TU-12s in a VC-4 is described in FIGS.7-10 of ITU-T standard recommendation G.707. The arrangement of theTU11s is given in FIGS. 7-11 of the same standard document. There is aclear correlation between time slots of a VC-4 container and thecorresponding TU-11s/TU-12s. If K designates the TUG-3 number (1 to 3),L the TUG-2 number (1 to 7) and M the TU-12 number (1 to 3) or TU-11number (1 to 4) then the columns of the VC-4 (1 to 261) occupied byTU-12 (K,L,M) are given as

10+(K−1)+3*(L−1)+21*(M−1)+63*(x−1) for x=1 to 4

[0074] and the columns occupied by a TU-11 (K,L,M) are given as

10+(K−1)+3*(L−1)+21*(M−1)+84*(x−1) for x=1 to 3.

[0075] 1. VC-4 POH

[0076] 2. fixed stuff—VC-4

[0077] 3. fixed stuff—VC-4

[0078] 4. fixed stuff—first TUG-3

[0079] 5. fixed stuff—second TUG-3

[0080] 6. fixed stuff—third TUG-3

[0081] 7. fixed stuff—first TUG-3

[0082] 8. fixed stuff—second TUG-3

[0083] 9. fixed stuff—third TUG-3

[0084] 10. 1. column oft. TU-11

[0085] 11. 1. column of 2. TU-11

[0086] 12. 1. column of 3. TU-11

[0087] 13. 1. column of 4. TU-11

[0088] . . .

[0089] . . .

[0090] 93. 1. column of 84. TU-11

[0091] 94. 2. column of 1. TU-11

[0092] . . .

[0093] . . .

[0094] 259. 3. column of 82. TU-11

[0095] 260. 3. column of 83. TU-11

[0096] 261. 3. column of 84. TU-11

[0097] The correlation of the TU-11s with the TUG-3s and TUG-2s is thena bit more complicated but not really relevant. The relation would be:

[0098] 1. TUG-3-1. TUG-2:1. TU-11, 22. TU-11, 43. TU-11. 64. TU-11

[0099] 1. TUG-3-2. TUG-2:4. TU-11, 25. TU-11. 46. TU-11, 67. TU-11

[0100] 1. TUG-3-3. TUG-2:7. TU-11, 28. TU-11. 49. TU-11, 70. TU-11

[0101] 1. TUG-3-4. TUG-2:10. TU-11, 31. TU-11, 52. TU-11, 73. TU-11

[0102] 1. TUG-3-5. TUG-2:13. TU-11, 34. TU-11, 55. TU-11, 76. TU-11

[0103] 1. TUG-3-6. TUG-2:16. TU-11, 37. TU-11, 58. TU-11, 79. TU-11

[0104] 1. TUG-3-7. TUG-2:19. TU-11, 40. TU-11, 61. TU-11, 82. TU-11

[0105] 2. TUG-3-1. TUG-2:2. TU-11, 23. TU-11, 44. TU-11, 65. TU-11

[0106] 2. TUG-3-2. TUG-2:5. TU-11, 26. TU-11, 47. TU-11, 68. TU-11

[0107] 2. TUG-3-3. TUG-2:8. TU-11, 29. TU-11, 50. TU-11, 71. TU-11

[0108] 2. TUG-3-4. TUG-2:11. TU-11, 32. TU-11, 53. TU-11, 74. TU-11

[0109] 2. TUG-3-5. TUG-2:14. TU-11, 35. TU-11, 56. TU-11, 77. TU-11

[0110] 2. TUG-3-6. TUG-2:17. TU-11, 38. TU-11, 59. TU-11, 80. TU-11

[0111] 2. TUG-3-7. TUG-2:20. TU-11, 41. TU-11 62. TU-11, 83. TU-11

[0112] 3. TUG-3-1. TUG-2:3. TU-11, 24. TU-11, 45. TU-11, 66. TU-11

[0113] 3. TUG-3-2. TUG-2:6. TU-11, 27. TU-11, 48. TU-11, 69. TU-11

[0114] 3. TUG-3-3. TUG-2:9. TU-11. 30. TU-11. 51. TU-11, 72. TU-11

[0115] 3. TUG-3-4. TUG-2:12. TU-11, 33. TU-11, 54. TU-11, 75. TU-11

[0116] 3. TUG-3-5. TUG-2:15. TU-11. 36. TU-11. 57. TU-11, 78. TU-11

[0117] 3. TUG-3-6. TUG-2:18. TU-11. 39. TU-11 60. TU-11, 81. TU-11

[0118] 3. TUG-3-7. TUG-2:21. TU-11, 42. TU-11, 63. TU-11, 84. TU-11

[0119] A corresponding relation holds in case of 63 TU-12s instead ofthe 84 TU-11s.

1. A device (100) for combining at least two data signals having a firstdata rate into a single data stream having a second data rate beinghigher than the first data rate for transmission on a shared medium orvice versa, said device comprises a) at least one port (102-108) forreceiving said at least two data signals, b) one port addressing unit(112) for extracting data from the data signals received by said ports(102-108), whereby said port addressing unit (112) is configured toplace the extracted data at predetermined positions in said single datastream to be transmitted on said shared medium, and c) at least onecontrol data insertion unit (120) for placing control data in saidsingle data stream, characterized by said one port addressing unit (112)and control data insertion unit (120) being configured such that saidextracting of data, said placing of extracted data and said placing ofcontrol data is performed per cycle and per port.
 2. The deviceaccording to claim 1, wherein said control data insertion unit (122) isconfigured to at least partly derive said control data from said datapositioned in said data stream.
 3. The device according to claim 1 or 2,wherein said control data insertion unit (122) is configured to placethe extracted data into said single data stream according to apredetermined transmission protocol, such as SONET or SDH.
 4. The deviceaccording to one of the preceding claims, wherein said port addressingunit (112) is configured to place the extracted data into said singledata stream according to a predetermined transmission protocol, such asSONET or SDH.
 5. The device according to one of the preceding claims,further comprising at least one buffer for buffering the data receivedby said at least one port.
 6. The device according to claim 5, whereinsaid at least one buffer is formed by a FIFO.
 7. The device according toclaim 5 or 6, wherein said buffer is configured to be used for pointergeneration in accordance with a predetermined transmission protocol,such as SONET or SDH.
 8. The device according to one of the precedingclaims, wherein the port addressing unit (112) is configured to extractdata from said at least one port in a predetermined order.
 9. The deviceaccording to one of the preceding claims, wherein all portions of saiddevice are driven by the same system clock.
 10. The device according toone of the preceding claims, wherein said control data insertion unit(122) is formed by a TU-11 or a TU-12 framing unit.
 11. The deviceaccording to claim 10, further comprising a TUG-2/TUG-4/VC-4 mappingunit (122) for mapping the data stream into one VC-4 container.
 12. Thedevice according to claim 11, further comprising an output port foroutputting a VC-4 data stream.
 13. The device according to claim 11 or12, further comprising a STM-N framing unit (126) for creating arespective data frame.
 14. A method for combining at least two datasignals having a first data rate into a single data stream having asecond data rate being higher than the first data rate for transmissionon a shared medium or vice versa, said method comprises the steps: a)receiving said at least two data signals, b) extracting data from thedata signals received by said ports c) characterized by the steps of d)placing the extracted data at predetermined positions in said singledata stream to be transmitted on said shared medium and placing controldata in said single data stream, and characterized in that steps b) tod) are done per cycle and per port.
 15. The method according to claim14, wherein the step of placing control data in said single data streamincludes deriving said control data from said data positioned in saiddata stream.
 16. The method according to claim 14 or 15, wherein thestep of placing control data in said single data stream includes placingthe extracted data into said single data stream according to apredetermined transmission protocol, such as SONET or SDH.
 17. Themethod according to one of the claims 14 to 16, wherein the step ofplacing the extracted data at predetermined positions in said singledata stream includes placing the extracted data into said single datastream according to a predetermined transmission protocol, such as SONETor SDH.
 18. The method according to one of the claims 14 to 17, furthercomprising the step of buffering the data received by said at least oneport.
 19. The method according to claim 18, wherein the step ofbuffering the data in done according to a FIFO-concept.
 20. The methodaccording to claim 18 or 19, wherein the step of buffering the dataincludes the step of generating a pointer in accordance with apredetermined transmission protocol, such as SONET or SDH.
 21. Themethod according to one of the preceding claims, wherein the step ofextracting data from the received data signals include the step ofextracting data from said at least one port in a predetermined order.22. A computer program product stored on a computer usable medium,comprising computer readable program means for causing a computer toperform a method according to anyone of the preceding claims 14 to 21.